In the semiconductor industry, there is a continuing trend toward higher device densities. To achieve these high densities there have been, and continue to be, efforts toward scaling down device dimensions (e.g., at sub-micron levels) on semiconductor wafers and to increase the number of layers of such devices on a chip. In order to accomplish such high device packing densities, smaller and smaller feature sizes are required. This may include the width and spacing of interconnecting lines, spacing and diameter of contact holes, and the surface geometry, such as corners and edges, of various features.
The increasing demand for miniaturization in the integrated circuits industry has led to an ever constant reduction in the size of integrated circuit (IC) components. Such reduction in the size of the components provides for lower cost manufacture due to smaller chip size and increased yield, as well as improved circuit performance in many instances. However, reduction in the size of some integrated circuit devices can lead to undesired results. For example, edges/corners of small components/layers are susceptible to failure in both wafer processing and device operation. The susceptibility of edges/corners of components/layers may cause undesirable current leakage.